Non-volatile memories using an error-correcting code ECC may be, for example, flash-NOR, flash-NAND, or EEPROM (electrically erasable and programmable) memories.
A non-volatile memory customarily comprises a memory plane, arranged in matrix fashion in rows and columns. Memory cells (or memory locations) are grouped into memory words and are capable of storing in a non-volatile manner a digital datum (otherwise called a bit) by charge retention in the floating gate of a floating-gate transistor.
Injections and extractions of charge in the floating gates by the Fowler-Nordheim effect make it possible to erase and to program the memory cells electrically.
In EEPROM memories, the memory words frequently comprise a byte. In EEPROM memories, the memory words frequently comprise a byte. In approaches using error-correcting codes, for example, for high-density EEPROM memories, the memory words can comprise several bytes, typically four, and a series of parity bits. Error-correcting codes such as a Hamming code make it possible to calculate the parity bits and to correct a possible error among the bytes or the parity bits of a memory word.
The writing of a digital datum in such a memory cell generally comprises a step of erasure followed by a step of programming of all the memory cells of one and the same memory word, or sometimes solely an erasure or programming step, as a function of the data to be written.
Memories of EEPROM type consequently have an internal granularity of the size of a memory word, but generally accept commands whose granularity is one single byte, so as to meet usage needs. The term granularity designates the smallest materially accessible unit of saved digital data.
Consequently, upon a command to write a size less than the internal granularity of the memory, it is necessary to recompose the data to be written with the old data stored in the memory plane so as to correspond to the internal granularity before implementing a cycle of writing at least one whole memory word. This recomposition comprises taking into account the new data to be written and the old data of the corresponding memory word which are stored in the memory plane, and requires a reading operation.
Generally, a memory of EEPROM type can, in a single write cycle, write at most a whole page comprising a number of bytes dependent on the size of the memory. For example, in a 16 Kbit memory, a page takes 16 bytes and it is possible to write from 1 to 16 bytes in a cycle, and, in a 4 Mbit memory, a page takes 512 bytes and it is possible to write from 1 to 512 bytes in a cycle.
FIG. 1 represents steps implemented during a customary writing of a memory of EEPROM type.
A preliminary step 99 corresponds to initializations of internal variables (i:=0, Rdmem:=0) and to a reinitialization of all the control gate latches CGL.
Step 101 corresponds to a start of reception of a write command and comprises a reception of a first byte NDi (i=0) to be written.
During the reception of the byte NDi (that is to say for a duration of eight clock ticks), a step of data recomposition 200 is systematically implemented. This step 200 corresponds to a reading of the old data stored in the memory plane, their possible correction, and their loading into an intermediate register ECCRG.
More precisely, and as represented by FIG. 2, the step of recomposing the data 200 comprises a reading 201 of the memory word in which the new data NDi are intended to be written. This reading 201 is done on the basis of the memory plane if the corresponding control gate latch CGL is reinitialized, otherwise on the basis of bit line latches BLL if the corresponding control gate latch CGL is initialized (see step 105). (“Reinitialization” and “initialization” are customarily designated by the respective terms “reset” and “set”, corresponding here to logical codes, for example, “0” and “1” respectively). The data read are loaded into the register ECCRG.
A correction 202 of a possible error is implemented by virtue of a mechanism of the Hamming code type. The data OD thus read and possibly corrected are thereafter loaded 203 into the intermediate register ECCRG.
This intermediate register ECCRG serves as output storage stage for the error correction logic, and as input for the bit line latches.
The architecture of the intermediate register ECCRG is analogous to a memory word architecture, that is to say that it comprises, for example, 4 bytes intended to receive data and a series of parity bits.
After the complete reception of the byte NDi (that is to say after the eight clock ticks), in the following step 102, the new byte NDi is loaded into the intermediate register ECCRG, by overwriting one of the four bytes OD of the register ECCRG.
A calculation of the new parity bits NP corresponding to the combination of the old data OD and of the new byte NDi is then implemented in a step 103.
The following step 104, consists in loading the bit line latches BLL with the data loaded in the intermediate register ECCRG.
Step 104 is followed by a step 105 of initialization of control gate latch CGL, representative of a loaded or unloaded state of the bit line latches BLL of the corresponding memory word. When the control gate latch of a memory word is initialized, the next reading of this memory word is done in the bit line latches and not in the memory plane.
These steps 104, 105 form part of a preliminary phase of a write cycle no in the course of which high-voltage pulses are applied in the memory cells so as to erase them and/or to program them according to the data contained in the bit line latches.
A test of end of reception 106 is carried out and, as long as the last byte has not been received and loaded into the corresponding bit line latches, steps 101 to 106 and 200 are repeated with the following consecutive bytes (107, 108).
When all the bytes to be written have been received, processed and loaded into the bit line latches, then the cycle of writing in the memory plane no is implemented during a common phase for all the data loaded in the bit line latches.
This type of conventional implementation exhibits the major drawback of being very expensive in terms of energy resources.
Indeed, this type of implementation comprises an unconditional reading operation for each byte to be written. This introduces non-negligible energy consumption.
Indeed, a majority of the energy consumption originates from the reading operations, each drawing a current of the order of 1.5 mA for a typical duration of 2 clock cycles (i.e., 5 μs at 400 kHz).
Consequently, for a write of 256 bytes, 256 reading operations, 256 error corrections and 256 calculations of parity bits are implemented. This corresponds to a consumption of a current of the order of 1.5 mA for an aggregate duration of 1.3 ms.
This energy expenditure is of the same order of magnitude as the energy expended during the cycle of writing in the memory plane.